Implementation Of Weighted Pseudorandom Test Pattern Generator For A Built In Self Test Architecture

Abstract

There is a significant demand for the functionality of the chip to be increased as submicron technology develops. The current generation's widespread IC production necessitates stringent testing to distinguish between the ideal chip and the flawed one. Verification For a full-scale verification to find product flaws, engineers must be knowledgeable of the chip's functionality. Traditional testing methods demand a significant amount of time and circuit complexity, making them unsuitable for the current generation. So, the automatic test pattern generation with great unpredictability between the test pattern generations becomes necessary. The randomness utilized to create the test pattern is produced by Galois Fields. A weighted test pattern generator has also been.