Design And Implementation Of Low Power, Area And High Performance 4 Bit Sequence Digital Counter

Abstract

The goals of the low power VLSI circuit are to decrease the system's energy footprint and power consumption while increasing the battery life and performance. The scaling architecture, often known as a counter, modifies the values of an operator depending on its previous state. It's possible that the counting procedure might provide time and frequency data. Clock power dissipation during standby is the primary reason of the excessive power consumption of scaling circuits. About one-third of a counter's total power is used up by the clock signal. In order to save energy, this research minimizes the number of switches used. The low power consumption of the counter is the result of work done to reduce the stress on the flip-flops. Combining TSPCL with SVL (Self-Controllable Voltage Level) is a viable option for accomplishing this goal. TSPCL can execute the Flip-Flop operation rapidly while using minimal power. The SVL technique is simpler since it requires fewer transistors and hence consumes less energy due to leakage current. The new model saves 27% more energy than the previous one. The proposed method locates feasible functions for cutting-edge, low-power devices.