An Efficient 2x2 And 4x4 SRAM Array By Using Compact Decoder For Low Power & Low Area Applications

Abstract

SRAM act us cache memory such as L2 and L3 in CPU and also used as interface between the CPU and DRAM. SRAM provides high operating speed and low power consumption due to not refreshing the memory content every time. It used transistor to store the data. But the cost is high and low memory capacity and low storage capacity.  In order to reduce the cost, the compact (i.e.) less number of transistors based SRAM array play vital role in cost effective memory design. The main aim of this work is to design a compact SRAM memory array for low power, low area and low cost applications.  Power optimization is performed by using various ways such as logical minimization using K-map, truth table reduction and Shannon’s theorem. In this work, truth table reduction scheme is used to design a compact AND gate of decoder for SRAM array. Also the compact 1 to 2 decoder and 2 to 4 decoder are used in 2x2 SRAM array and 4x4 SRAM array by using 6T SRAM cell. Also CMOS 22nm nanotechnology is used for transistor scaling scheme. From the analysis, the 6T SRAM cell based 2x2 and 4x4 SRAM array with compact decoder offers low cost, low resource utilization and low power consumption than the regular decoder based SRAM array.